ZBasic System Library
ShiftOutEx(dataPin, clkPin, bitCnt, val, flags)
ShiftOutEx(dataPin, clkPin, bitCnt, val, flags, bitTime)
The pin used to output data.
The pin used to output a clocking signal.
The number of bits to shift out (1 to 16).
The value to shift out.
Flag bits controlling the operation.
The optional duration of each bit in ticks (see description).
This function can be used to output data to a synchronous serial device like a shift register. The pin
specified for output will be made an output but the pin specified for the clock signal must already be an
output and be at the desired initial logic level. The flags parameter controls how the shifting process is
performed as described in the table below.
Control Flag Definitions
xx xx xx x0
xx xx xx x1
Fastest possible bit time
xx xx x0 xx
Use the provided bitTime parameter
xx xx x1 xx
Normal data pin output
xx xx 0x xx
Open drain data pin output
xx xx 1x xx
The remaining bits are currently undefined but may be employed in the future. For compatibility, the
undefined bits should always be zero.
For each of the number of bits specified, the data pin will be set to the state of the corresponding bit in the
val parameter beginning with the either the most significant bit first or the least significant bit first
depending on bit 0 of the flags parameter. Then the clock line will be pulsed by changing its logic level
Note that if a data width of fewer than 16 data bits is specified, the bits to be shifted out must be properly
aligned in the value provided. If MSB order is specified, the data bits must be positioned in the most
significant bits of the value provided. If LSB order is specified, the data bits must be positioned in the
least significant bits of the value provided.
If the flags parameter so specifies, the bitTime parameter value will be used to control the bit rate of
the shifting process. The units of the bitTime parameter are, by default, 1 CPU cycle (67.8ns at
14.7MHz). However, Register.TimerSpeed1 may be changed to adjust the controlling clock speed.
If the bitTime parameter is not provided or if the value given is zero, the shifting will occur at the
Due to processing overhead the minimum bit time in the controlled speed mode is approximately 60 CPU
cycles (4µS at 14.7MHz). Attempting faster bit times in the controlled speed mode will produce undefined
results. Without speed control, the bit time is approximately 32 CPU cycles (2.2µS at 14.7MHz). Note
that the duty cycle of the clock signal will be closer to 50% in the controlled speed mode. Without speed
control, the active clock phase can be as little as 20% of the period.