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147 OpenI2C Type Subroutine Invocation OpenI2C(channel, sdaPin, sclPin) or OpenI2C(channel, sdaPin, sclPin, bitRate) Parameter Method Type Description channel ByVal Byte The I2C channel to open (0-4). sdaPin ByVal Byte The pin for the I2C data (SDA) signal. sclPin ByVal Byte The pin for the I2C clock (SCL) signal. bitRate ByVal integral The optional clock speed designation, see discussion. Discussion This subroutine prepares an I2C channel for use. Five channels are supported, numbered 0 through 4. Channel zero uses the onboard hardware I2C controller while channels 1 through 4 are implemented in software. The I2C implementation does not support multi-master arbitration when operating in Master mode. Slave clock stretching is supported on both hardware and software channels. For channel 0, the sdaPin and sclPin parameters are ignored since the hardware uses specific pins for the SDA and SCL signals (e.g. Port C, bits 1 and 0, respectively). For channels 1-4, the sdaPin and sclPin parameters specify the pins to use for the data and clock signals, respectively. In both cases, the clock and data pins are automatically configured for I2C operation. The I2C protocol requires pullup resistors on both of the lines, the value of which depends on characteristics of your system. A typical value is in the range of 1.5K to 4.7K. The optional bitRate parameter allows you to control the speed of the data interchange. If the parameter is not given, the default speed is 100KHz. Each I2C device has a maximum clock rate at which it will operate reliably; check the datasheet of your selected device to determine the maximum rate. The interpretation of the value of the bitRate parameter differs for channel 0 and channels 1-4. The tables below specify the values to use for several common clock speeds. I2C Channel 0 Clock Speeds bitRate Value Approximate Clock Speed Notes 140 50KHz 66 100KHz Standard Low Speed, default speed 29 200KHz 11 388KHz Closest to Standard High Speed (400KHz) 10 410KHz Highest supported speed I2C Channels 1-4 Clock Speeds¹ bitRate Value Approximate Clock Speed Notes 295 50KHz 148 100KHz Standard Low Speed, default speed 74 200KHz 59 250KHz Highest supported speed 1 The values given assume the default setting of Register.TimerSpeed1. For channel 0, the bitRate parameter is a composite of two values: the value in the lower 8 bits is known as BR and is written to the processor’s TWBR register. The low two bits of the high byte select a clock divisor according to the table below. The clock speed of the hardware channel is given by the