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ZBasic System Library 220 ZX Microcontroller Family PWM Type Subroutine Invocation PWM(channel, dutyCycle) PWM(channel, dutyCycle, status) Parameter Method Type Description channel ByVal Byte The channel to use for PWM generation. dutyCycle ByVal Single or integral The desired duty cycle. status ByRef Boolean The variable to receive the status value. Discussion This subroutine begins or modifies the generation of a 16-bit PWM signal on the specified channel. The channel must have been previously prepared for PWM generation by calling OpenPWM(). PWM generation is performed using one of the CPU’s 16-bit timers, the number of which varies depending on the ZX model. The table below indicates the output pin for each PWM supported channel. Output Pins for 16-bit PWM Channel Numbers ZX Models 1 2 3 4 5 6 ZX-24, ZX-24a, ZX-24p, ZX-24n 26, D.5 27, D.4 - - - - ZX-40, ZX-40a, ZX-40p, ZX-40n 19, D.5 18, D.4 - - - - ZX-44, ZX-44a, ZX-44p, ZX-44n 14, D.5 13, D.4 - - - - ZX-24r, ZX-24s 26, D.5 27, D.4 B.6 B.7 - - ZX-40r, ZX-40s 19, D.5 18, D.4 7, B.6 8, B.7 - - ZX-44r, ZX-44s 14, D.5 13, D.4 2, B.6 3, B.7 - - ZX-24e, ZX-24ae, ZX-24ne, ZX-24pe, ZX-24nu, ZX-24pu 15, D.5 16, D.4 - - - - ZX-328n, ZX-328l 15, B.1 16, B.2 - - - - ZX-32n, ZX-32l 13, B.1 14, B.2 - - - - ZX-1281, ZX-1281n 15, B.5 16, B.6 17, B.7 5, E.3 6, E.4 7, E.5 ZX-1280, ZX-1280n 24, B.5 25, B.6 26, B.7 5, E.3 6, E.4 7, E.5 ZX-24x 26, D.0 27, D.1 D.4 D.5 12, C.0 11, C.1 ZX-32a4 20, D.0 21, D.1 24. D.4 25, D.5 10, C.0 11, C.1 ZX-128a1 25, D.0 26, D.1 27, D.4 28, D.5 15, C.0 16, C.1 ZX-128e, ZX-128ne, ZX-1281e, ZX-1281ne 23, B.5 22, B.6 21, B.7 17, E.3 16, E.4 15, E.5 ZX-328nu 12, B.1 13, B.2 - - - - ZX Models 7 8 9 10 11 12 ZX-1280, ZX-1280n 15, H.3 16, H.4 17, H.5 38, L.3 39, L.4 40, L.5 ZX-24x 10, C.2 9, C.3 25, E.0 17, E.1 18, E.2 19, E.3 ZX-32a4 12, C.2 13, C.3 28, E.0 29, E.1 30, E.2 31, E.3 ZX-128a1 17, C.2 18, C.3 35, E.0 36, E.1 37, E.2 38, E.3 ZX Models 13 14 15 16 17 18 19 20 ZX-128a1 39, E.4 40, E.5 45, F.0 46, F.1 47, F.2 48, F.3 49, F.4 50, F.5 The dutyCycle parameter specifies the desired duty cycle of the generated signal, expressing the percentage of time that the PWM signal will be at the logic 1 state. If the supplied parameter is of type Single, the value is in percent with a resolution of 0.01%. If the supplied parameter is integral, the units