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ZBasic System Library 299 ZX Microcontroller Family The window mode of the analog comparator utilizes both channels of the comparator, with channel 0 representing the high limit of the window and channel 1 representing the low limit of the window. The mode value to use differs depending on whether single channel or window mode is being used, see the tables below. Analog Comparator Interrupt Mode Values – Single Channel Mode Value Built-in Constant Interrupt Trigger &H00 zxAnalogCompChange Comparator output rising edge or falling edge. &H02 zxAnalogCompFalling Comparator output falling edge. &H03 zxAnalogCompRising Comparator output rising edge. Analog Comparator Interrupt Mode Values – Window Mode Value Interrupt Trigger &H00 Input signal above the window. &H01 Input signal inside the window. &H02 Input signal below the window. &H03 Input signal outside the window. Operation For all forms, when the trigger condition occurs an interrupt will be generated and the task awaiting the interrupt will rise to the highest priority. This will cause an immediate task switch meaning that the next instruction that executes will be the one following the WaitForInterrupt() invocation. Note that if another task performs an action that causes interrupts to be disabled, response to the interrupt will be delayed until interrupts are re-enabled. The fact that the current task is locked does not prevent the interrupt task from executing next. If two or more interrupts occur simultaneously, the task awaiting the highest priority interrupt is activated first. For VM mode devices, the priorities of the various interrupts are given in the table below. VM Mode Devices Interrupt Priority (highest to lowest) Interrupt 0 Interrupt 1 Interrupt 2 Analog Comparator Interrupt Interrupt 3 Interrupt 4 Interrupt 5 Interrupt 6 Interrupt 7 Pin Change Interrupt, Port A Pin Change Interrupt, Port B Pin Change Interrupt, Port C Pin Change Interrupt, Port D Pin Change Interrupt, Port E Pin Change Interrupt, Port J Pin Change Interrupt, Port K For native mode devices, the interrupt priority corresponds to the order of the entries in the processor’s interrupt vector table: the lower the vector number the higher the priority. Consult the ATmega or ATxmega processor datasheet for more information on this topic. Note that a task awaiting an interrupt will exhibit some latency between the occurence of the interrupt and when the waiting task begins execution. The latency depends on a number of factors including the specific instruction being executed at the time of the interrupt and the number and frequency of system interrupts that need to be handled. Instructions that may take a long time to execute such as