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ZBasic System Library
9
ZX Microcontroller Family
ZX-1281, ZX-1281n
No
10, B.0
ZX-1280, ZX-1280n
No
19, B.0
ZX-32a4
No
24, D.4
23, C.4
ZX-128a1
No
29, D.4
19, C.4
39, E.4
49, F.4
ZX-24e, ZX-24ae, ZX-24pe, ZX-24pu
Yes
24, B.4
ZX-24ne, ZX-24nu, ZX-24ru, ZX-24su
No
24, B.4
ZX-128e, ZX-128ne, ZX-1281e, ZX-1281ne
No
28, B.0
ZX-24xu
No
16, D.4
8, C.4
ZX-328nu
No
13, B.2
It is important to note that even for the devices that do not use the external SPI EEPROM, the SPI CS pin
cannot be used as a general purpose input if the SPI bus is used in your application. This restriction is an
artifact of the design of the CPU’s SPI controller. The SPI CS pin can, however, be used as a general
purpose output.
Analog-to-Digital Converters
Most ZX devices support up to 8 analog inputs. These inputs may be fed to the internal analog-to-digital
converter (ADC) or they may be used to perform analog level comparisons. The I/O port containing the
analog inputs varies by ZX device as indicated in the table below. The System Library routines
GetADC() and ADCtoCom1() use the ADC. The analog comparator is used by WaitForInterrupt()
when configured to await an analog comparator event.
Analog Input Ports by CPU Type
Underlying CPU Type
Analog Port 1
Analog Port 2
mega32, mega644, mega644P, mega1284P
Port A
-
mega328P
Port C
-
mega128, mega1281
Port F
-
mega1280
Port F
Port K
xmega128A1, xmega32A4
Port A
Port B
Interrupts
Some of the System Library routines disable interrupts in order to achieve the precise timing that is
required. Having interrupts disabled for long periods of time can interfere with the operation of other parts
of the system that use interrupts like task management, serial I/O and the real time clock. In most cases,
the System Library routines have been implemented to keep track of real time clock interrupts that should
have occurred during the time interrupts are disabled and then the RTC is updated at the end of the
operation. This strategy avoids the problem of the RTC losing time.
Unfortunately, there is no way to similarly protect the serial I/O process. You can reduce the impact of
having interrupts disabled with respect to serial output by ensuring that all serial output queues are empty
before calling a System Library routine that disables interrupts. This is not as critical for a hardware-
based serial channel (e.g. Com1) as it is for the software-based serial channels Com3 to Com6. There is
no way, however, to work around the problem of serial input data arriving while interrupts are disabled.
The hardware-based serial channels will store one received character and hold it while interrupts are
disabled but if a second character arrives while interrupts are disabled it will be lost. Channels 3-6 rely on
interrupts for every bit received so the situation is much more problematic. In this case, having interrupts
disabled for longer than approximately one-third of the bit time will likely cause garbled input if a
character’s transmit time overlaps the period when interrupts are disabled. For characters being
transmitted by channels 3-6, having interrupts disabled for more than about 10% of the bit time may
cause the receiver to lose synchronization.
For reference purposes, the table below indicates which I/O routines disable interrupts for the duration of
their execution. See the individual descriptions for more detailed information.
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