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ZBasic System Library
183
ZX Microcontroller Family
For devices that have multiple SPI controllers (e.g. xmega-based devices), the most significant byte of the
flags parameter specifies the index of the SPI controller to use (0=PortD, 1=PortC, 2=PortE, 3=PortF).
See the tables below for information about which pins of each port are used for the SPI control/data pins.
The rxDelay parameter, which defaults to zero if not present, specifies the amount of time to delay
before beginning the SPI cycle for each byte received, if any, during the second half of the SPICmd()
process. See the description of SPICmd() for more details.
SPI Clock and Data Pins for the Primary SPI Controller (Index=0)
ZX Models
SCK
MISO
MOSI
ZX-24, ZX-24a, ZX-24p, ZX-24n, ZX-24r, ZX-24s¹
B.7
B.6
B.5
ZX-40, ZX-40a, ZX-40p, ZX-40n, ZX-40r, ZX-40s
8, B.7
7, B.6
6, B.5
ZX-44, ZX-44a, ZX-44p, ZX-44n, ZX-44r, ZX-44s
3, B.7
2, B.6
1, B.5
ZX-328n, ZX-328l
19, B.5
18, B.4
17, B.3
ZX-32n, ZX-32l
17, B.5
16, B.4
15, B.3
ZX-1281, ZX-1281n
11, B.1
13, B.3
12, B.2
ZX-1280, ZX-1280n
20, B.1
22, B.3
21, B.2
ZX-24x¹
D.7
D.6
D.5
ZX-32a4
27, D.7
26, D.6
25, D.5
ZX-128a1
32, D.7
31, D.6
30, D.5
ZX-24e, ZX-24ae, ZX-24ne, ZX-24pe,
ZX-24nu, ZX-24pu, ZX-24ru, ZX-24su
21, B.7
22, B.6
23, B.5
ZX-128e, ZX-128ne, ZX-1281e, ZX-1281ne
27, B.1
25, B.3
26, B.2
ZX-328nu
16, B.5
15, B.4
14, B.3
ZX-24xu
13, D.7
14, D.6
15, D.5
¹ The SPI pins are found along the edge of the board between pins 1 and 24.
SPI Clock and Data Pins for the Available Alternate SPI Controllers
ZX Models
Index
SCK
MISO
MOSI
ZX-24x, ZX-24xu
1
5. C.7
6, C.6
7, C.5
ZX-32a4
1
17, C.7
16, C.6
15, C.5
ZX-128a1
1
2
3
22, C.7
42, E.7
52, F.7
21, C.6
41, E.6
51, F.6
20, C.5
40, E.5
50, F.5
Caution
For ZX devices that use an external SPI EEPROM for user program storage, you must avoid doing
anything that will interfere with the SPI commands to that device. SPI communication by direct
manipulation of the processor SPI control registers is not supported and may cause your program to
malfunction.
Compatibility
BasicX does not support the double speed option, the active high chip select, the optional rxDelay
parameter, or the bit-bang mode. The same is true for ZX devices based on the ATmega32 processor.
See Also
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