Page 40 of 346 Start Back Next End ZBasic System Library 28 ZBasic Microcontrollers Chan 2, Pin 25 (B.3) Supported DAC Channels for Generic Target Devices ZX Devices DACB DACA xmega16a4, xmega32a4 Chan 1, Pin 6 (B.2) Chan 2, Pin 7 (B.3) - xmega16d4, xmega32d4, xmega64d3, xmega128d3, xmega192d3, xmega256d3 - - xmega64a3, xmega128a3, xmega256a3, xmega256a3b Chan 1, Pin 7 (B.2) Chan 2, Pin 8 (B.3) - xmega64a1, xmega128a1 Chan 1, Pin 7 (B.2) Chan 2, Pin 8 (B.3) Chan 3, Pin 97 (A.2) Chan 4, Pin 98 (A.3) Note, particularly, that the ATxmega can produce two analog outputs from a single DAC. In the table above, channels 1 and 2 are the two outputs from one DAC and channels 3 and 4 are the two outputs from the second DAC (if available). In order to use the second channel on a given DAC, the first channel must have been opened in dual output mode (see the mode details in the description of OpenDAC). Also note that using both outputs from a DAC will result in analog levels with significantly more noise due to the sample-and-hold and automatic refresh circuitry employed. For this reason, it is generally recommended to use single output per DAC. Interrupts in General Some of the System Library routines disable interrupts in order to achieve the precise timing that is required. Having interrupts disabled for long periods of time can interfere with the operation of other parts of the system that use interrupts like task management, serial I/O and the real time clock. In most cases, the System Library routines have been implemented to keep track of real time clock interrupts that should have occurred during the time interrupts are disabled and then the RTC is updated at the end of the operation. This strategy avoids the problem of the RTC losing time. However, there is a limit to the amount of time that missed RTC timer interrupts can be accurately tracked, that limit being 65535 divided by the RTC fast tick frequency. See Section 3 for more information about the RTC fast tick frequency. Unfortunately, there is no way to similarly protect the serial I/O process. You can reduce the impact of having interrupts disabled with respect to serial output by ensuring that all serial output queues are empty before calling a System Library routine that disables interrupts. This is not as critical for a hardware- based serial channel (e.g. Com1) as it is for the software-based serial channels Com3 to Com6. There is no way, however, to work around the problem of serial input data arriving while interrupts are disabled. The hardware-based serial channels will store one received character and hold it while interrupts are disabled but if a second character arrives while interrupts are disabled it will be lost. Channels 3-6 rely on interrupts for every bit received so the situation is much more problematic. In this case, having interrupts disabled for longer than approximately one-third of the bit time will likely cause garbled input if a character’s transmit time overlaps the period when interrupts are disabled. For characters being transmitted by channels 3-6, having interrupts disabled for more than about 10% of the bit time may cause the receiver to lose synchronization. For reference purposes, the table below indicates which I/O routines disable interrupts for the duration of their execution. See the individual descriptions for more detailed information.