Suggested Enhancement for Logical Pin Numbers

[mikep]

The only real difference between the various flavors of ZX chip is the physical pin numbers which are mapped to the actual ATmega32 pin numbers inside the ZBasic virtual machine. The TargetCPU option is a directive to the compiler which results in mapping explicit pin designations such as A.6 to the physical pin number.

However one requirement is to have the same ZBasic program whatever the ZX chip being used. This allows people to distribute their programs in compiled form without needing to worry about which ZX chip it will be run on (except in the case where function is used that is not available on the ZX-24 because of the more limited physical pinout).

Enter the idea of logical pin designations where the compiler uses the TargetCPU option to map physical pin numbers to logical ones. For example C.6 could be mapped to 150 (128+8+8+6). The compiler when compiling for a ZX-24 (the default) can convert pin 19 to A.1 and therefore to logical pin 129 (128+1). If using the Option TargetCPU ZX40 then pin 19 is converted to D.5 (logical pin 157). If using Option TargetCPU ZX44 then pin 19 is converted to C.0 (logical pin 146).

Both the compiler and internal VM for each chip need to be changed. The reason for setting the MSB of the logical pin number (128) is so that programs compiled with previous versions of the compiler still run. The VM can easily use a different mapping table for the logical pins 128 to 159.

[dkinzer]

This change is on the list of things to do. The plan is to use the MSB to indicate that the remaining 7 bits specify a port/pin combination. Three bits are needed to specify a bit number and the other 4 bits specify the port (A=0, etc.).

[mikep]

The change for logical pin numbering becomes obvious once you add more chips to the mix such as ZX-44. I'm glad to see you already thought of this