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victorf
Joined: 01 Jan 2006
Posts: 342
Location: Schenectady, New York
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Posted: 10 January 2006, 14:16 PM Post subject: Ramtron FM25256 Memory |
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First the disclaimer; I am a SPI beginner:
I would like to interface a FM25256 FRAM device to a Z-24's SPI buss. Has anyone done this and, if so, would you share your code?  A Ramton app note suggests a 10k pullup be placed between the /CS pin and VDD. Opinions 
Also, some documents discussing SPI use the terms SDO and SDI and some use the terms MOSI and MISO. What is the relation between these sets of terms? My guess; MOSI = SDI and MISO = SDO. 
Any enlightenment will be appreciated.
Vic |
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DH*
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Posted: 10 January 2006, 14:36 PM Post subject: |
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Peter Anderson has code for interfacing external SPI EEPROM to a BX-24 on his web pages.
http://www.phanderson.com/basicx/index.html
You can probably adapt it to the ZX-24.
I designed a small circuit board to hold an SPI EEPROM (SOIC8) and 10K pullup which can piggyback on a BX-24. If Don wants the Gerbers I can provide them. |
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spamiam
Joined: 13 Nov 2005
Posts: 664
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Posted: 10 January 2006, 15:06 PM Post subject: Re: Ramtron FM25256 Memory |
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| victorf wrote: | First the disclaimer; I am a SPI beginner:
I would like to interface a FM25256 FRAM device to a Z-24's SPI buss. Has anyone done this and, if so, would you share your code? A Ramton app note suggests a 10k pullup be placed between the /CS pin and VDD. Opinions
Also, some documents discussing SPI use the terms SDO and SDI and some use the terms MOSI and MISO. What is the relation between these sets of terms? My guess; MOSI = SDI and MISO = SDO.
Any enlightenment will be appreciated.
Vic |
Yes, I believe that the SDI == MOSI, and SDO == MISO.
Yes, a 10k pull up on the /CS is a good idea. It took me a while to understand that LOW on the /CS means that chip is selected.
The good thing about the SPI FRAM (if my memory serves) is that the FRAM will suspend its transaction if it loses CS. This is important bacause the hardware SPI is used to run the ZX processor too. You need to be able to interleave ZX eeprom access with your FRAM multibyte transactions.
It is reasonably easy to hook up the FRAM to the SPI bus. You simply need to be able to arbitrate between the EEPROM and the FRAM.
I have not really thougt in-depth about these arbitration issues. I think you might need to use some sort of NAND gate between your own CS pin dedicated to the FRAM, and the EEPROM's /CS pin. I think you might need to have your program RAISE the FRAM CS pin to make it active, and that combined with the high EEPROM /CS pin will allow the NAND to go low, and thereby activate the /CS pin of the FRAM.
I do not think that a simple NAND will do the job, but i am sure a smart poerson here will chime in.
I think that this is a really neat application. Probably worthy of an APPNOTE one you iron out the details.
To the other poster who has gerbers of a FRAM SIP board: I'd be interested in seeing them! I could work out a layout in EAGLE freeware so anyone could make them. Also, I eventually will be sending out an order for a PCB, and I will have room for additional stuff on a small panel.
-Tony |
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DH*
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Posted: 10 January 2006, 15:31 PM Post subject: |
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| Quote: | | To the other poster who has gerbers of a FRAM SIP board: I'd be interested in seeing them! I could work out a layout in EAGLE freeware so anyone could make them. Also, I eventually will be sending out an order for a PCB, and I will have room for additional stuff on a small panel. |
See Files.
In the description I forgot to mention that you need to solder a wire from /CS to whatever pin you want to use. I planned to use the red LED. |
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cloxwerx
Joined: 01 Dec 2005
Posts: 37
Location: Tucson, Arizona
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Posted: 10 January 2006, 16:26 PM Post subject: |
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As a word of encouragement, I have used the FRAM FM25W256-S with a BX-35 as a direct drop-in EEPROM and it has worked fine. That doesn't address the EEPROM/SPI second device problem, but it's a starting point that shows that the device can work. It is also much faster when doing PUTEEPROM calls. My test with 1000 bytes showed the FRAM to accomplish this is 1/75th of the time compared to the stock EEPROM. I haven't tried any of this with the ZX series.
Dennis |
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victorf
Joined: 01 Jan 2006
Posts: 342
Location: Schenectady, New York
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Posted: 10 January 2006, 17:56 PM Post subject: |
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With regard to the arbitation issue between the EEPROM and FRAM access, when does the ZX-24 access its EEPROM? Does it do this "when it feels like it" or only under user software control. If it is not possible to reliably use the SPI feature of the ZX then I do not understand why the feature is exposed. There are plenty of SPI devices out there that users might like to attach to their controller. There must be a reliable way to do this! Can the SPI functionality be done strictly in software?
BTW: I plan to use a PortC pin to be the CS line for the FRAM.
Any enlightenment will be appreciated.
Vic |
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dkinzer
Site Admin
Joined: 03 Sep 2005
Posts: 2499
Location: Portland, OR
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Posted: 10 January 2006, 18:38 PM Post subject: |
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| Quote: | | With regard to the arbitation issue between the EEPROM and FRAM access, when does the ZX-24 access its EEPROM? Does it do this "when it feels like it" or only under user software control. |
The external EEPROM contains the instruction codes for your program. The ZX fetches an instruction byte and, if necessary, additional bytes comprising the instruction and then executes the instruction. Then, this process repeats.
To fetch a byte from the EEPROM, it is necessary to send the EEPROM a "read" instruction, followed by the high and low address bytes and then the byte at that address can be read back. This means that 32 SPI clock cycles elapse before the byte is returned. Fortunately, it not necessary to send the read instruction and address for every byte retrieved. As long as the EEPROM's chip select is kept low, you can read the next sequential byte by performing another SPI cycle - 8 clocks.
The ZX firmware exploits this characteristic by keeping the EEPROM's chip select low as long as it can. This works well for linear code execution because there is essentially an instruction pipeline set up and the next instruction byte is already available by the time that the ZX needs it. When a jump instruction occurs, the ZX determines whether it "cheaper" to read unneeded bytes sequentially to get to the required next byte or to terminate the current read cycle and restart it at the new address.
Since the MOSI, MISO and SCK lines are shared among all devices using the hardware SPI interface, if the user code executes an SPICmd(), the EEPROM must be deselected. The chip select for the channel involved in the SPICmd() is asserted prior to the beginning of the SPI data transfer and deasserted at the end. The ZX then needs to read the next instruction to execute so it performs the sequence described above.
You can see, then, that SPI operations are interleaved between the external EEPROM and the user SPI devices. Many/most SPI devices will work with this interleaving but some will not. You'll need to read the datasheet for the device in question to determine if it can be interfaced using SPICmd(). If the desired operation can be performed using only the data written by and read by one SPICmd() invocation or if the device retains its state information even if it is deselected, then the device is compatible.
If a device cannot be interfaced using SPICmd(), the alternative is to use a bit-bang implementation of SPI. You can find one such implementation on Tom Handley's site. |
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spamiam
Joined: 13 Nov 2005
Posts: 664
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Posted: 10 January 2006, 18:44 PM Post subject: |
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I do think a NAND will do it as long as the ZX pin is used opposite to the /CS of the EEPROM
Here is the truth table. (I can't get it to preserve my formatting, hope it looks understandable)
LOGIC TABLE
EEPROM /CS ZX-FRAM CSPIN NAND (to FRAM /CS)
_______________________________________________________
LOW (selected) HIGH (selected) HIGH (not selected)
LOW (selected) LOW (not selected) HIGH (not selected)
HIGH (not selected) HIGH (selected) LOW (selected)
HIGH (not selected) LOW (not selected) HIGH (not selected) |
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spamiam
Joined: 13 Nov 2005
Posts: 664
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Posted: 10 January 2006, 18:58 PM Post subject: |
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| dkinzer wrote: | | You'll need to read the datasheet for the device in question to determine if it can be interfaced using SPICmd(). If the desired operation can be performed using only the data written by and read by one SPICmd() invocation or if the device retains its state information even if it is deselected, then the device is compatible. |
Oh yes, I forgot that the SPICmd() specifies the CS pin to be used (as I now recollect). Therefore you do not need to arbitrate the CS with the EEPROM yourself. Thankfully. You just need to get the MOSI/MISO/CLK from the SPI header), and your own /CS signal from elsewhere on the ZX. So no need for any NAND arbitration at all!
The FRAM does allow interleaving, as I remember. As I said, the SD/MMC cards do not. This is a major limitation because the bit banged data rate is about 3KHz, while the HW SPI much faster. I have never actually tested the data rate, but the SPI hardware itself can run at 8MHz, I think.
With some extra pins and a demux chip, you can have multiple FRAMS working at the same time.
If you do not need more than 400Kbps, then you can use the simpler I2C bus for FRAM too. It is still much faster than EEPROM.
-Tony |
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dkinzer
Site Admin
Joined: 03 Sep 2005
Posts: 2499
Location: Portland, OR
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Posted: 10 January 2006, 19:16 PM Post subject: |
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| Quote: | | Here is the truth table. (I can't get it to preserve my formatting, hope it looks understandable) |
Use the "Code" button to preserve formatting. What this does is it wraps the text with the words "code" and "/code" inside square brackets.
Voila!
| Code: | LOGIC TABLE
EEPROM /CS ZX-FRAM CSPIN NAND (to FRAM /CS)
_______________________________________________________
LOW (selected) HIGH (selected) HIGH (not selected)
LOW (selected) LOW (not selected) HIGH (not selected)
HIGH (not selected) HIGH (selected) LOW (selected)
HIGH (not selected) LOW (not selected) HIGH (not selected) |
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