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victorf
Joined: 01 Jan 2006
Posts: 342
Location: Schenectady, New York
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dkinzer
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Joined: 03 Sep 2005
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Location: Portland, OR
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Posted: 29 March 2006, 18:54 PM Post subject: |
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Your concern about tying outputs together is well-founded. There is also the drawback that it has four possible jumper configurations and only two of them could be correct. One way to fix this issue is to use the first alternate circuit below. The disadvantage that it has is that the input signal has more loads to drive in the non-inverted case.
A second alternative is shown below. This one always presents the same load to the input signal. The disadvantage is the need for an additional component type. However, depending on the other requirements of your circuit, you may be able to use the remaining XOR gates as inverters (by tying one input high) and thereby eliminate one inverter package.
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victorf
Joined: 01 Jan 2006
Posts: 342
Location: Schenectady, New York
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Posted: 29 March 2006, 19:49 PM Post subject: |
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Thanks for the reply.
I like both solutions from an aesthetic viewpoint  and from your comments, I would select the invert2 solution. The addition of one resistor does not bother me. Would a value of 10k be satisfatory?
Vic
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dkinzer
Site Admin
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Location: Portland, OR
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Posted: 29 March 2006, 22:10 PM Post subject: |
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| Quote: | | I like both solutions... |
There are, of course, many other possible solutions. For example:
1) Use an NPN transistor in place of the inverter. This may be preferable if you have no spare inverter available and are cramped for space on your board. A transistor and two resistors may take less space than a DIP-14 package. If you're using SMT devices, the inverter or XOR gate may be preferable.
2) Use a 2-to-1 multiplexer. This may be useful if you have to switch several signals based on a jumper setting. Instead of having separate jumpers for each signal a quad 2-to-1 multiplexer like the 74LS157 would allow you to select between 4 pairs of signals with a single jumper.
| Quote: | | Would a value of 10k [for the pullup resistor] be satisfatory? |
This depends to some extent on which logic family you're using. For the 74LS series, I prefer 2.2K to 4.7K but for any of the CMOS families (e.g. 74HC, 74HCT, etc.) 10K is fine. For devices used in an electrically noisy environment I would favor lower values over higher values. For a typical prototype or experimental circuit the value doesn't really matter very much.
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Is there a better solution?
