Hardware SPI to MMC card?

[spamiam]

I have a functioning bit-bang interface to a MMC card. I want to see if I can get it faster with hardware SPI. But the MMC cards seem to need pretty low level ability to interract with the SPI pins.

1) For instance, to initialize the MMC card, you are supposed to send 10 bytes with the CS pin DESELECTED.

I assume that other transactions on the SPI bus will have MORE that 10 bytes sent (i.e. to the EEPROM), so this part is probably already done for me.

But how do I _ensure_ that there were 10 bytes-worth of clocks with CS deselected? Do I define another SPI channel with pin 0 as the CS pin, then send 10 bytes on the dummy channel?



2) Similarly, when all the transactions are done, then CS is deselected and a byte is sent over the SPI bus. Do I do this the same way?



3) does anyone have experience with sharing the SPI bus with something like the EEPROM? Does the MMC card object to CS being deasserted after the card is initialized, but before other MMC transactions like a read or write?

-Tony

[dkinzer]

Your idea of using an alternate SPI channel would seem to meet the requirements of both (1) and (2).

Regarding the CS going inactive, I expect that there are some "transactions", so to speak, that must be done while keeping CS asserted. I haven't looked at the SD/MMC protocol in detail but the EEPROM is like this. For example, you send it a Write command and an address and then you send it a series of bytes to be written. As long as you keep CS asserted you can keep writing bytes until the page limit is reached. At the page boundary you must deassert CS and then initiate another cycle (read or write). On Read cycles you can read continuously irrespective of the page boundaries.

The SD/MMC protocol may have similar sequences where you must keep CS asserted, others where you must deassert CS and still others where you may do either.

[spamiam]

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[spamiam]

[dkinzer]

[spamiam]

You are right, it DOES seem pointless to be unable to share the SPI bus.

I will try to see how it works as-is running off the SPI bus, knowing that it will enter an idle state between MMC accesses.

I am just sure what the significance of going idle is.....

The manufacturers are not very free with their info about the functions of the SD/MMC cards.

I am especially interested in trying to get it to work w/o support logic for 2 reasons. 1) simplicity, 2) I only have 4000-series logic on hand, except inverters! They are rather SLOW! As I look at the SPI clock activity with my scope, I see that the 7MHZ clock frequency is painfully close the the max bandwidth of the AND gate I am testing! The specs say that rise time is 100uS. MAX speed would be 10Mhz, and probably half that is better.

I will try checking other forums about sharing the SPI bus.

-Tony