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Acceptable Voltage Ripple

 
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Don_Kirby



Joined: 15 Oct 2006
Posts: 329
Location: Long Island, New York
Posted: 11 June 2007, 0:08 AM    Post subject: Acceptable Voltage Ripple Reply with quote
In designing power supplies for uC projects, are there guidelines regarding acceptable levels of voltage ripple on the 5 volt rail? For example, I see no mention of ripple in any of the Atmel datasheets, yet there has to be a limit, which when exceeded, causes problems.

Obviously, we should all design power supplies that produce negligible ripple at their output, but just out of curiosity, what's the limit?

-Don
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dkinzer
Site Admin


Joined: 03 Sep 2005
Posts: 2593
Location: Portland, OR
Posted: 11 June 2007, 0:46 AM    Post subject: Re: Acceptable Voltage Ripple Reply with quote
Don_Kirby wrote:
[...]are there guidelines regarding acceptable levels of voltage ripple on the 5 volt rail?
The absolute maximum ripple would be that which causes the power supply voltage to fall below the largest minimum, or rise above the smallest maximum, supply specification for all the components in the system. You would do well, however, to keep the ripple less than that. As with most things, it's a design tradeoff. You could probably get it pretty small by using a 1 farad capacitor but that is likely impractical for most situations.

The AVR chips used for ZX devices specify the supply range as 4.5V to 5.5V.
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Don_Kirby



Joined: 15 Oct 2006
Posts: 329
Location: Long Island, New York
Posted: 11 June 2007, 1:58 AM    Post subject: Reply with quote
Don, using your example circuit for a Mega32 based ZX, how do you suppose ripple will affect the A/D performance? I'd guess that even if the device operates with a large amount of ripple, it would surely have an adverse affect on A/D performance.

-Don
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dkinzer
Site Admin


Joined: 03 Sep 2005
Posts: 2593
Location: Portland, OR
Posted: 11 June 2007, 2:05 AM    Post subject: Reply with quote
Don_Kirby wrote:
[...]how do you suppose ripple will affect the A/D performance?
It is not Vcc but Aref that affects A/D conversion (assuming that you're using GetADC). If there is noise or ripple on Aref your conversion results will have an uncertainty based on the deviation of Aref from the 5.0 volt value that is used in your conversion calculations.

Increasing the size of the capacitor on Aref, or the size of the inductor feeding it, may help significantly because the current draw into Aref is fairly small. It is essentially a high impedance input.
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dkinzer
Site Admin


Joined: 03 Sep 2005
Posts: 2593
Location: Portland, OR
Posted: 11 June 2007, 19:27 PM    Post subject: Reply with quote
My previous reply was not quite correct. Improving the conditioning on Avcc (not Aref as previously indicated) will improve the accuracy of the A/D readings. It is important to note that the Port A I/O pins (on a meg32 and mega644) are powered by Avcc in addition to the A/D circuitry. Filtering on Aref is still important but the 10nF capacitor is probably sufficient. It can be increased, however, if desired.
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