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pjc30943
Joined: 02 Dec 2005
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Posted: 02 December 2005, 18:02 PM Post subject: SPI Clock |
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The SPI clock appears to be ~=2V pk-pk. Is this assuming a 3.3V system? Admittedly my scope at home is only 5MHz (don't laugh...), so it may just not have enough bandwidth to see the full signal. I'll take it in later tonight to use our 5ghz scopes, but was hoping to get something going by then.
Bit banged spi works fine, as does ShiftIn/OutEx, but I can't get the HW spi to go. I wonder if the clock magnitude has anything to do with this, if indeed it is not 5V pk-pk. |
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dkinzer
Site Admin
Joined: 03 Sep 2005
Location: Portland, OR
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Posted: 02 December 2005, 19:26 PM Post subject: |
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With the program below, you should see a square wave on SCK with voltage swing of nearly zero to nearly Vcc (pin 21 voltage) and a period of about 130nS. The rise time (10% to 90%) is measured on my 'scope at about 4nS. The rise time actually could be faster than this since my 'scope is only 100MHz (Tek 465).
| Code: | Sub Main()
Do
Loop
End Sub
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You might try observing the SCK signal using a logic probe. It will likely not flash with only a 2V excursion. Alternately, you could connect SCK to a 4-bit counter and look at the carry out. If it is being clocked you should see a signal at 1/16th the frequency on the carry out.
Note that the SPI signals presented to your circuit are exactly those that are used to access the on-board EEPROM containing your program. If those signals were way out of spec, it is quite likely that the download verification would fail and your program wouldn't run.
I have used an external AT25256A as a test device to confirm that the SPI functions of the System Library work. I haven't used SPI to access other types of devices but I believe that others have done so successfully.
What SPI device are you connecting? |
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pjc30943
Joined: 02 Dec 2005
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Posted: 02 December 2005, 21:00 PM Post subject: |
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You might recall my posts from the BX list, and the outcome (thank you; this uP is quite nice). So this is the same device, I'm using a few AD7706's. I too have already tried the 32 clocks, as you also had suggested. There was no discernable effect.
However, I can talk perfectly with bit-banged, or with the 16-bit shiftIOEx of the ZX. It would just be optimal to use HW.
I am using idle low, and have the clock going through an inverter (transistor). I also used a '14 to make sure it just wasn't some edge-transition-time problem with the generic transistor.
If the other two methods work, in the ideal world I should find the transition easy; since I don't: way to go, self!  |
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dkinzer
Site Admin
Joined: 03 Sep 2005
Location: Portland, OR
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Posted: 02 December 2005, 22:04 PM Post subject: |
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| Quote: | | ...I'm using a few AD7706's. |
What clock rate are you using? The datasheet that I saw specified 2.5MHz maximum. You will need to use a bit rate of f/16 to get below that. However, you should be able to use double speed mode - that would give you a clock speed of about 1.8MHz.
| Quote: | | However, I can talk perfectly with bit-banged |
That would be well below 2.5MHz, of course. |
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dkinzer
Site Admin
Joined: 03 Sep 2005
Location: Portland, OR
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Posted: 02 December 2005, 22:25 PM Post subject: |
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I was confused. That is the maximum frequency of the device's master clock. The specified minimum high and low time of SCLK is 100nS, equivalent to 5MHz.
One other specification that needs to be looked at is the setup time from CS asserted to the rising clock edge. The datasheet calls for 120nS. I'll check to see what the timing actually is. | Quote: | | Update: I measured the time from CS low to the first clock edge as 2.02uS so that's not a problem. |
The timing diagrams for the device seems to suggest that it wants to use SPI mode 3. If you are inverting the clock, that would be mode 1 at the ZX-24. The timing diagram shows the clock idling high, a falling edge and then sampling the data on the rising edge. |
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pjc30943
Joined: 02 Dec 2005
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Posted: 02 December 2005, 23:03 PM Post subject: |
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Thanks Don for taking the time to look at this.
I've always run at f/128, which is what I started with for testing. Yes, it is mode 3, and if I use a low idling clk, that is mode 1 (which is what the ZX system uses for its eeprom). So inverting this clock, per your recommendation on the bx forum, should give mode 3...so what I have should work...
Since the clock does indeed look to be 0->Vcc using my faster scope, it appears to be a logistical issue on my end, so I won't take up any more ZX space with this subject  Thanks though for helping with it. |
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dkinzer
Site Admin
Joined: 03 Sep 2005
Location: Portland, OR
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Posted: 02 December 2005, 23:16 PM Post subject: |
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| Quote: | | Yes, it is mode 3, and if I use a low idling clk, that is mode 1 (which is what the ZX system uses for its eeprom). |
I'm quite certain that the ZX uses mode 0 as does the BX series. To confirm, run this program:
| Code: | Sub Main()
Debug.Print "SPCR=0x"; CStrHex(Register.SPCR)
End Sub
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G Herzog
Joined: 26 Mar 2006
Location: Kaohsiung
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Posted: 26 March 2006, 16:27 PM Post subject: |
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| Is MODE 0, the only SPI mode [of the 4] available on the BasicZ? |
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dkinzer
Site Admin
Joined: 03 Sep 2005
Location: Portland, OR
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Posted: 26 March 2006, 16:58 PM Post subject: |
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| Quote: | | Is MODE 0, the only SPI mode [of the 4] available |
If you're referring to OpenSPI and SPICmd, all four modes are available. The mode is selected using the 'flags' parameter to OpenSPI. The following table shows the correspondence between the flag bits and the SPI modes:
| Code: | flags value SPI Mode
xx xx 00 xx 0
xx xx 01 xx 1
xx xx 10 xx 2
xx xx 11 xx 3 |
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