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ShiftinEx clock phase

 
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pjc30943



Joined: 02 Dec 2005
Posts: 220
Posted: 13 December 2005, 4:12 AM    Post subject: ShiftinEx clock phase Reply with quote
During which part of the clock cycle does ShiftInEx look at data?

I'd guess it to be the same as with ShiftOutEx (i.e. sample data on the trailing clock edge), but have been burned by even more simple assumptions...
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dkinzer
Site Admin


Joined: 03 Sep 2005
Posts: 2499
Location: Portland, OR
Posted: 13 December 2005, 5:35 AM    Post subject: Reply with quote
Quote:
During which part of the clock cycle does ShiftInEx look at data?


It is selectable whether it is sampled before or after the leading edge of the clock. In both cases, the clock output is assumed to be initially in the desired "idle state". If bit 1 of the 'flags' parameter is zero, the clock line changes state and then the input is sampled. Otherwise, the input is sampled and then the clock line changes state. Then, for both cases, the clock line is changed back to the idle state.

Other 'flags' bits control whether the clocking is done as fast as possible or if it is "throttled" and whether the shifting is LSB first or MSB first.
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